Recently, semiconductor devices such as LSI have been required to have higher density in order to meet requirements for reducing the mounting space or for improving the processing rate. As an example of a technology that achieves the higher density, there has been known a multilayer wiring technology of manufacturing a multilayer substrate, such as a three-dimensional LSI or the like, by stacking multiple wiring substrates.
According to the multilayer wiring technology, a through-via-hole in which a conductive material such as copper (Cu) is buried is typically formed to penetrate each wiring substrate in order to obtain electrical connection between the wiring substrates.
When producing the wiring substrate, Cu is used as the conductive material and is buried in a recess of the substrate. In this case, a barrier film serving as a Cu diffusion suppressing film needs to be formed within the recess, and a seed film needs to be formed on this barrier film by electroless Cu plating. Accordingly, a wiring volume of a wiring layer may be reduced or a void may be generated in the buried Cu. Meanwhile, there has been developed a technique in which a catalyst is supplied within the recess of the substrate and a Co-based metal, instead of Cu, is buried within the recess by the electroless plating to be used as a wiring layer. In this case, the Co-based alloy within the recess is buried in a bottom-up shape on a lower electrode which is provided on a bottom surface of the recess.
When supplying the catalyst within the recess of the substrate, however, this catalyst may also adhere to a sidewall of the recess or a surface of the substrate. In such a case, the Co-based alloy may grow on the catalyst attached to the surface of the substrate as well, and a plating layer of the Co-based alloy formed on the surface of the substrate remains as an unnecessary plating layer. This unnecessary plating layer needs to be removed afterwards by using a chemical mechanical polishing method.